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ltc3113 1 3113f typical application description 3a low noise buck-boost dc/dc converter the ltc ? 3113 is a wide v in range, highly ef? cient, ? xed frequency, buck-boost dc/dc converter that operates from input voltages above, below or equal to the output voltage. the topology incorporated in the ic provides low noise operation, making it well suited for rf and precision measurement applications. the ltc3113 can deliver up to 3a of continuous output current to satisfy the most demanding applications. higher output current is possible in stepdown (buck) mode. integrated low r ds(on) power mosfets and a programmable switching frequency up to 2mhz result in a compact solution footprint. selectable burst mode operation improves ef? ciency at light loads. other features include <1a shutdown current, integrated soft-start, short-circuit protection, current limit and ther- mal overload protection. the ltc3113 is housed in the thermally enhanced 16-lead (4mm 5mm 0.75mm) dfn and 20-lead tssop packages. features applications n regulated output with input voltage above, below or equal to the output voltage n 1.8v to 5.5v input and output voltage range n 3a continuous output current v in > 3.0v, v out = 3.8v n 1.5a continuous output current for v in 1.8v, v out = 3.3v n single inductor n low noise buck-boost architecture n up to 96% ef? ciency n programmable frequency from 300khz to 2mhz n selectable burst mode ? operation n output disconnect in shutdown n shutdown current: <1a n internal soft-start n small, thermally enhanced 16-lead (4mm 5mm 0.75mm) dfn package and 20-lead tssop package n wireless modems n backup power systems n portable inventory terminals n portable barcode readers n portable instrumentation ef? ciency vs input voltage sw1 v in v out ltc3113 2.2h run 47f 100f v out 3.8v 3a v in 3v to 4.2v burst off on pwm burst fb vc 49.9k 845k 680pf 12pf 90.9k rt sw2 sgnd pgnd 158k 3113 ta01a 6.49k 47pf l , lt, ltc, ltm, burst mode, linear technology and the linear logo are registered trademarks and no r sense , powerpath are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. li-ion to 3.8v/3a input voltage (v) 1.5 50 efficiency (%) 55 65 70 75 100 85 2.0 2.5 3113 ta01b 60 90 95 80 3.0 3.5 4.0 4.5 5.0 5.5 i load = 1a v out = 3.8v i load = 3a
ltc3113 2 3113f v in , v out , sw1, sw2 voltage (dc) .............. C0.3v to 6v sw1, sw2 voltage, pulsed (<100ns) (note 4) ............7v vc, run, burst voltage ............................. C0.3v to 6v fb ................................................................C0.3v to v in rt voltage.................................................... C0.3v to 1v order information lead free finish tape and reel part marking* package description temperature range ltc3113edhd#pbf ltc3113edhd#trpbf 3113 16-lead (5mm 4mm) plastic dfn C40c to 125c ltc3113idhd#pbf ltc3113idhd#trpbf 3113 16-lead (5mm 4mm) plastic dfn C40c to 125c ltc3113efe#pbf ltc3113efe#trpbf ltc3113fe 20-lead plastic tssop C40c to 125c ltc3113ife#pbf ltc3113ife#trpbf ltc3113fe 20-lead plastic tssop C40c to 125c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www .linear.com/tapeandreel/ absolute maximum ratings (notes 1, 3) operating junction temperature range (notes 2, 5) ............................................ C40c to 125c maximum junction temperature........................... 125c storage temperature range ................... C65c to 150c lead temperature (soldering, 10 sec) tssop .............................................................. 300c 16 15 14 13 12 11 10 9 17 pgnd 1 2 3 4 5 6 7 8 sw2 sw2 sw1 sw1 sw1 run fb vc v out v out v in v in v in sgnd burst rt top view dhd package 16-lead (5mm s 4mm) plastic dfn t jmax = 125c, ja = 36.5c/w, jc = 3.6c/w exposed pad (pin 17) is pgnd, must be soldered to pcb fe package 20-lead plastic tssop 1 2 3 4 5 6 7 8 9 10 top view 20 19 18 17 16 15 14 13 12 11 pgnd v out v out v in v in v in sgnd burst rt pgnd pgnd sw2 sw2 sw1 sw1 sw1 run fb vc pgnd 21 pgnd t jmax = 125c, ja = 31.5c/w, jc = 4.1c/w exposed pad (pin 21) is pgnd, must be soldered to pcb pin configuration
ltc3113 3 3113f note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3113 is tested under pulsed load conditions such that t j t a . the ltc3113e is guaranteed to meet performance speci? cations from 0c to 85c junction temperature. speci? cations over the C40c to 125c operating temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3113i is guaranteed to meet performance speci? cations over the C40c to 125c operating junction temperature range. electrical characteristics the l denotes speci? cations which apply over the full junction temperature range, otherwise speci? cations are at t a = 25c (note 2). v in = 3.3v, v out = 3.8v unless otherwise noted. parameter condition min typ max units input operating range l 1.8 5.5 v output voltage adjust range l 1.8 5.5 v feedback voltage v burst = 0v l 588 600 612 mv feedback input current v fb = 0.7v 050 na quiescent currentCburst mode operation v burst = 3.3v 40 55 a quiescent currentCshutdown v out = 0v, v run = 0v, not including switch leakage 0.1 1 a quiescent currentCactive v fb = 0.7v, v burst = 0v, r t = 90.9k 300 500 a input current limit l 5.8 7.8 9.8 a peak current limit 6.5 11.1 16.0 a burst mode peak current limit 0.9 1.9 2.9 a reverse current limit C1.6 C1 C0.4 a nmos switch leakage switch b, sw1 = 5.5v, v in = 5.5v, v out = 5.5v switch c, sw2 = 5.5v, v in = 5.5v, v out = 5.5v 0.01 0.01 10 10 a a pmos switch leakage switch a, v in = 5.5v, v out = 5.5v, sw1 = 0v switch d, v in = 5.5v, v out = 5.5v, sw2 = 0v 0.01 0.01 20 20 a a nmos switch on-resistance switch b, v out = 3.8v switch c, v out = 3.8v 25 35 m m pmos switch on-resistance switch a, v in = 3.3v switch d, v out = 3.8v 30 40 m m maximum duty cycle boost (% switch c on) buck (% switch a on) l l 80 100 90 % % minimum duty cycle l 0% frequency accuracy r t = 90.9k l 0.8 1 1.2 mhz error amp avol 100 db error amp source current v c = 0v, v fb = 0v 500 a error amp sink current v c = 1.2v, v fb = 0.7v 160 a burst input logic threshold l 0.3 0.7 1.2 v burst input current v burst = 5.5v 01 a run input logic threshold l 0.3 0.7 1.2 v run input current v run = 5.5v 01 a soft-start time 2ms note 3: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. the maximum rated junction temperature will be exceeded when the protection is active. continuous operation above the speci? ed absolute maximum operating junction temperature may impair device reliability or permanently damage the device. note 4: voltage transients on the switch pins beyond the dc limit speci? ed in the absolute maximum ratings are non-disruptive to normal operation when using good layout practices, as shown on the demo board or described in the data sheet and application notes. note 5: the junction temperature (t j in c) is calculated from the ambient temperature (t a in c) and the power dissipation (p d in watts) as follows: t j = t a + (p d ) ? ( ja c/w)
ltc3113 4 3113f typical performance characteristics burst mode no-load input current vs v in burst mode no-load input current vs temperature pwm mode no-load input current vs v in normalized p-channel switch resistance vs v in ef? ciency 3.3v 10% to 3.8v ef? ciency 1.8v, 3.6v, 5.5v to 3.8v normalized n-channel switch resistance vs v in feedback voltage vs temperature maximum load current in pwm mode vs v in (input current limit 5.8a) (t a = 25c, v in = 3.3v, v out = 3.8v unless otherwise speci? ed) temperature (c) C45 input current (a) 40 50 60 15 55 75 95 3113 g04 30 20 C25 C5 35 115 10 0 temperatature (c) C45 feedback voltage (v) 0.599 0.600 0.601 15 55 3113 g08 0.598 0.597 C25 C5 35 75 95 115 0.596 0.595 load current (a) 60 efficiency (%) 70 80 90 100 0.001 0.1 1 10 3113 g01 50 0.01 v in = 2.97v v in = 3.3v v in = 3.63v v in = 2.97v burst v in = 3.3v burst v in = 3.63v burst load current (a) 60 efficiency (%) 70 80 90 100 0.001 0.1 1 10 3113 g02 50 0.01 v in = 1.8v v in = 3.6v v in = 5.5v v in = 1.8v burst v in = 3.6v burst v in = 5.5v burst v in (v) 1.5 0 input current (a) 10 30 40 50 100 70 2.5 3.0 3.5 3113 g03 20 80 90 60 2.0 4.0 4.5 5.0 5.5 v out = 5.5v v out = 1.8v v out = 3.8v v in (v) 1.5 0 input current (ma) 10 20 30 40 2.5 3.5 4.5 5.5 3113 g05 50 60 2.0 3.0 4.0 5.0 v out = 5.5v v out = 3.8v v out = 1.8v v in (v) 0.7 normalized p-channel switch resistance 0.9 1.1 1.4 1.3 0.8 1.0 1.2 2345 3113 g06 6 1.51 2.5 3.5 4.5 5.5 t = 125c t = 25c t = C40c v in (v) 0.6 normalized n-channel switch resistance 0.8 1.0 1.6 1.4 0.7 0.9 1.2 1.5 1.3 1.1 2345 3113 g07 6 1.51 2.5 3.5 4.5 5.5 t = 125c t = 25c t = C40c v in (v) 1.5 1 maximum load current (a) 2 3 4 5 2.5 3.5 4.5 5.5 3113 g09 6 2.0 3.0 4.0 5.0
ltc3113 5 3113f maximum load current in burst mode operation vs v in (burst mode peak current limit 0.9a) output voltage regulation vs load current load step, 0a to 3a output voltage ripple in burst mode operation typical performance characteristics (t a = 25c, v in = 3.3v, v out = 3.8v unless otherwise speci? ed) output voltage ripple in pwm mode burst to pwm mode transient soft-start v in (v) 1.5 maximum load current (ma) 200 250 4.5 3113 g10 150 100 2.5 3.5 2.0 5.0 3.0 4.0 5.5 50 0 300 load current (a) C0.8 output voltage regulation (%) C0.6 C0.4 0 C0.2 0.0001 0.01 0.1 10 3113 g11 C1.0 0.001 1 pwm mode burst mode operation i load 2a/div v out 200mv/div 100s/div back page typical application 3113 g12 inductor current 1a/div v out 20mv/div 20s/div i load = 50ma front page typical application 3113 g14 v out 20mv/div v out 20mv/div v out 20mv/div 1s/div i load = 1a 3113 g14 v in = 3.3v v in = 4v v in = 4.55v v out 50mv/div burst 2v/div 500s/div i load = 50ma 3113 g15 front page typical application v out 2v/div run 5v/div 500s/div v in = 3.3v v out = 3.8v c out = 100f 3113 g16 normalized input current limit vs temperature (7.8a typical) normalized peak current limit vs temperature (11.1a typical) temperature (c) 0.90 normalized input current limit 1.00 1.10 0.95 1.05 C25 15 55 95 3113 g17 115 C45 C5 35 75 temperature (c) C45 normalized peak current limit 1.05 3113 g18 0.95 0.90 C5 35 75 95 C25 15 55 115 1.10 1.00
ltc3113 6 3113f typical performance characteristics (t a = 25c, v in = 3.3v, v out = 3.8v unless otherwise speci? ed) minimum start-up voltage vs temperature oscillator frequency vs r t temperature (c) C45 1.685 start-up voltage (v) 1.687 1.691 1.693 1.695 1.705 1.699 C5 35 55 3113 g19 1.689 1.701 1.703 1.697 C25 15 75 95 115 r t (k) 050 0 oscillator frequency (mhz) 1.0 2.5 100 200 250 3113 g20 0.5 2.0 1.5 150 300 350 oscillator frequency (mhz) 0.25 C6 reverve current limit (a) C5 C3 C2 C1 0.65 1.05 1.25 3113 g21 C4 0.45 1.45 1.65 1.85 0 0.85 v out pulled up to 5.5v l = 2.2h negative inductor current vs oscillator frequency junction temperature rise vs continuous load current for v out = 1.8v load current (a) 0 0 junction temperature rise (c) 10 20 30 40 60 0.5 1 1.5 2 2.5 3 3.5 3113 g22 4 4.5 50 v in = 1.8v v in = 2.4v v in = 3.3v v in = 5.5v junction temperature rise vs continuous load current for v out = 3.3v load current (a) 0 0 junction temperature rise (c) 10 20 30 40 60 0.5 1 1.5 2 3113 g23 2.5 3 3.5 4 4.5 50 v in = 1.8v v in = 2.4v v in = 3.3v v in = 5.5v junction temperature rise vs continuous load current for v out = 3.8v load current (a) 0 0 junction temperature rise (c) 10 20 30 40 60 0.5 1 1.5 2 2.5 3 3.5 3113 g24 4 4.5 50 v in = 1.8v v in = 2.4v v in = 3.3v v in = 5.5v junction temperature rise vs continuous load current for v out = 5.5v load current (a) 0 0 junction temperature rise (c) 10 20 30 40 60 0.5 1 1.5 2 3113 g25 2.5 3 3.5 50 v in = 1.8v v in = 2.4v v in = 3.3v v in = 5.5v
ltc3113 7 3113f pin functions v out (pins 1, 2/pins 2, 3): buck-boost output voltage. a low esr capacitor should be placed from v out to pgnd. the capacitor should be placed as close to the ic as pos- sible and have a short return path to ground. v in (pins 3, 4, 5/pins 4, 5, 6): power input for the converter. a 47f or larger bypass capacitor should be connected between v in and pgnd. the bypass capacitor should located as close to v in and pgnd as possible and should via directly to the ground plane. sgnd (pin 6/pin 7): signal ground. terminate the fre- quency setting resistor and output voltage divider to sgnd. burst (pin 7/pin 8): pulse width modulation/burst mode selection input. forcing this pin low causes the switching converter to operate in low noise ? xed frequency pwm mode. forcing this pin high enables constant burst mode operation for the converter. during burst mode operation, the converter can only support a reduced maximum load current. rt (pin 8/pin 9): programs the frequency of the internal oscillator. connect a resistor from rt to ground (sgnd). the r t resistor value for a given frequency is given by the following equation. r t ? 90 fmhz () k () vc (pin 9/pin 12): error amp output. an r-c network is connected from this pin to fb for loop compensation. refer to the closing the feedback loop section for component selection guidelines. fb (pin 10/pin 13): feedback voltage for the buck-boost converter derived from a resistor divider on the buck- boost output voltage. the buck-boost output voltage is given by the following equation: v out = 0.600 1 + r2 r1 ? ? ? ? ? ? v () where r1 is a resistor connected between fb and sgnd, and r2 is a resistor connected between fb and v out . the buck-boost output voltage can be adjusted from 1.8v to 5.5v. run (pin 11/pin 14): active high converter enable in- put. applying a voltage <0.3v to this pin shuts down the ltc3113. applying a voltage >1.2v to this pin enables the ltc3113. sw1 (pins 12, 13, 14/pins 15, 16, 17): switch pin where internal switches a and b are connected. connect the inductor from sw1 to sw2. minimize trace length to reduce emi. sw2 (pins 15, 16/pins 18, 19): switch pin where internal switches c and d are connected. connect the inductor from sw1 to sw2. minimize trace length to reduce emi. pgnd (exposed pad pin 17/pins 1, 10, 11, 20, exposed pad pin 21): the exposed pad must be soldered to the pcb and electrically connected to ground through the shortest and lowest impedance connection possible. in most applications the bulk of the heat ? ow out of the ltc3113 is through this pad, so printed circuit board design has an impact on the thermal performance of the part. see the pcb layout and thermal considerations section for more details. (dfn/tssop)
ltc3113 8 3113f detailed block diagram + C 1.6v sleep uvlo + C + C + C + + C 11.1a v in swa v in 1.8v to 5.5v swd swc reverse current limit swb sw1 sw2 2.2h peak current limit pwm comparators error amp 7.8a C1.0a input current limit soft-start 0.6v fb v out vc r z 49.9k c p1 680pf c p2 12pf 1 = on 0 = off pwm logic and output phasing burst mode control run logic gate drivers and anticross conduction osc run run sgnd rt r t 90.9k 1 = burst 0 = pwm burst + C + r1 158k 3113 bd r2 845k r z2 6.49k c z1 47pf c l 100f + C 10 9 11 6 pgnd 17 7 8 3 13 12 14 15 16 1 2 4 5 (dfn package)
ltc3113 9 3113f operation introduction the ltc3113 is a low noise, high power synchronous buck-boost dc/dc converter optimized for demanding applications. the ltc3113 utilizes a proprietary switching algorithm, which allows its output voltage to be regulated above, below or equal to the input voltage. the error ampli- ? er output (vc) determines the output duty cycle of each switch. the low r ds(on) , low gate charge, synchronous power switches provide high frequency pulse width modu- lation control. high ef? ciency is achieved at light loads when burst mode operation is commanded. low noise fixed frequency operation oscillator the frequency of operation can be programmed between 300khz and 2mhz by an external resistor from the rt pin to ground, according to the following equation: r t ? 90 fmhz () k () error ampli? er the error ampli? er is a high gain voltage mode ampli- ? er. the loop compensation components are con? gured around the ampli? er (from fb to vc) to obtain stable converter operation. for improved bandwidth, an addi- tional rc feedforward network can be placed across the upper feedback divider resistor. refer to the applications information section of this data sheet under closing the feedback loop for information on selecting compensation type and components. current limit operation the buck-boost converter has two current limit circuits. the primary current limit is an average current limit cir- cuit which sources current into fb to reduce the output voltage, should the input current exceed 7.8a. due to the high gain of the feedback loop, the injected current forces the error ampli? er output to decrease until the average current through switch a decreases approximately to the current limit value. the average current limit utilizes the error ampli? er in an active state and thereby provides a smooth recovery with little overshoot once the current limit fault condition is removed. since the current limit is based on the average current through switch a, the peak inductor current in current limit will have a dependency on the duty cycle (i.e., on the input and output voltages) in the overcurrent condition. for this current limit feature to be most effective, the thevenin resistance from fb to ground should exceed 100k. the speed of the average current limit circuit is limited by the dynamics of the error ampli? er. on a hard output short, it is possible for the inductor current to increase substantially beyond current limit before the average cur- rent limit circuit would react. for this reason, there is a second current limit circuit which turns off switch a if the current ever exceeds approximately 142% of the average current limit value. this provides additional protection in the case of an instantaneous hard output short. should the output voltage become less then 1.2v nomi- nally, both the current limits are reduced compared to the normal operating current limits. reverse current limit during ? xed frequency operation, a reverse-current com- parator on switch d monitors the current entering v out . when this current exceeds 1a (typical) switch d will be turned off for the remainder of the switching cycle. this feature protects the buck-boost converter from excessive reverse current if the buck-boost output is held above the regulation voltage by an external source. in applications where the oscillator frequency is pro- grammed above 1mhz and the output voltage is held above its programmed regulation value, reverse currents greater than 1a (typical) may be observed. in conjunction with oscillator frequencies higher than 1mhz, higher output voltages will also increase the magnitude of observed reverse current. refer to the negative inductor current vs oscillator frequency graph in the typical performance characteristics section for typical variations.
ltc3113 10 3113f operation internal soft-start the ltc3113 buck-boost converter has an independent internal soft-start circuit with a nominal duration of 2ms. the converter remains in regulation during soft-start and will therefore respond to output load transients which occur during this time. in addition, the output voltage rise time has minimal dependency on the size of the output capaci- tor or load current during start-up. during soft-start, the buck-boost is forced into pwm mode operation regardless of the state of the burst pin. thermal shutdown if the die temperature exceeds 155c the ltc3113 buck- boost converter will be disabled. all power devices are turned off and the switch nodes will be forced into a high impedance state. the soft-start circuit for the converter is reset during thermal shutdown to provide a smooth recovery once the overtemperature condition is eliminated. when the die temperature drops to approximately 145c the ltc3113 will restart. for recommendations regarding thermal design of the ltc3113 pcb, refer to the pcb ther- mal considerations section in applications information. undervoltage lockout if the supply voltage decreases below 1.6v (typical) then the ltc3113 buck-boost converter will be disabled and all power devices are turned off. the soft-start circuit is reset during undervoltage lockout to provide a smooth restart once the input voltage rises above 1.7v (typical) the undervoltage lockout increasing threshold. when operating the ltc3113 at low input voltages, care must be taken under heavy loads to prevent the part from cycling into and out of uvlo. when operating at low input voltages the voltage drop created by the source resistance can trigger the uvlo, resetting the part. operation near the undervoltage lockout is not recommended, but if require- ments dictate, the source resistance should be less than 100mv/i in(max) (where i in(max) is the maximum input current) to ensure proper operation. inductor damping when the ltc3113 is in burst operation and sleep mode, active circuits damp the inductor voltage through 165 (typical) impedance from both sw1 and sw2 to ground minimizing emi. pwm mode operation when the burst pin is held low, the ltc3113 buck- boost converter operates in a ? xed-frequency pulse width modulation (pwm) mode using voltage mode control. full output current is only available in pwm mode. a proprietary switching algorithm allows the converter to transition between buck, buck-boost, and boost modes without discontinuity in inductor current. the switch topology for the buck-boost converter is shown in figure 1. figure 1. buck-boost switch topology a b d c 3113 f01 l v in v out when the input voltage is signi? cantly greater than the output voltage, the buck-boost converter operates in buck mode. switch d turns on continuously and switch c remains off. switches a and b are pulse width modu- lated to produce the required duty cycle to support the output regulation voltage. as the input voltage decreases, switch a remains on for a larger portion of the switching cycle. when the duty cycle reaches approximately 85%, the switch pair ac begins turning on for a small fraction of the switching period. as the input voltage decreases further, the ac switch pair remains on for longer durations and the duration of the bd phase decreases proportionally. as the input voltage drops below the output voltage, the
ltc3113 11 3113f ac phase will eventually increase to the point that there is no longer any bd phase. at this point, switch a remains on continuously while switch pair cd is pulse width modu- lated to obtain the desired output voltage. at this point, the converter is operating solely in boost mode. this switching algorithm provides a seamless transition between operating modes and eliminates discontinuities in average inductor current, inductor current ripple, and loop transfer function throughout all three operational modes. these advantages result in increased ef? ciency and stability in comparison to the traditional four-switch buck-boost converters. burst mode operation with the burst pin held high, the buck-boost converter operates utilizing a variable frequency switching algorithm designed to improve ef? ciency at light load and reduce the standby current at zero load. in burst mode operation, the inductor is charged with ? xed peak amplitude current pulses and as a result only a fraction of the maximum output current can be delivered when in this mode. these current pulses are repeated as often as necessary to maintain the output regulation voltage. the maximum output current, i max , which can be supplied in burst mode operation is dependent upon the input and output voltage as given by the following formula: i max ? i pk 2 ? v in v in + v out ? a () where i pk is the burst mode peak current limit in amps and is the ef? ciency. if the buck-boost load exceeds the maximum burst mode current capability, the output rail will lose regulation. in burst mode operation, the error ampli? er is con? gured in a low power mode of operation and used to hold the compensation pin, vc, to reduce transients that may oc- cur during transitions from burst mode to pwm mode operation. operation
ltc3113 12 3113f applications information the basic ltc3113 application circuit is shown as the typical application on the front page of this data sheet. the external component selection is dependent upon the required performance of the ic in each particular appli- cation given considerations and trade-offs such as pcb area, output voltage, output current, output ripple voltage and ef? ciency. this section of the data sheet provides some basic guidelines and considerations to aid in the selection of external components and the design of the application circuit. output voltage programming the buck-boost output voltage is set via an external resistor divider connected to the fb pin as shown in figure 2. formulas, where f is the frequency in mhz and l is the inductance in h: i l,p-p,buck = v out f?l v in ?v out v in ? ? ? ? ? ? a () i l,p-p,boost = v in f?l v out ?v in v out ? ? ? ? ? ? a () to ensure operation without triggering the reverse current comparator under no load conditions it is recommended that the peak-to-peak inductor ripple not exceed 800ma taking into account the maximum reverse current limit of C0.4a speci? ed in the electrical characteristics section. utilizing this recommendation for applications operating at a switching frequency of 300khz requires a minimum inductance of 6.8h, similarly an application operation at a frequency of 2mhz would require a minimum of 1h. in addition to affecting output current ripple, the value of the inductor can also impact the stability of the feedback loop. in boost and buck-boost mode, the converter transfer function has a right half plane zero at a frequency that is inversely proportional to the value of the inductor. as a result, a large inductor can move this zero to a frequency that is low enough to degrade the phase margin of the feedback loop. in addition to affecting the ef? ciency of the buck-boost converter, the inductor dc resistance can also impact the maximum output capability of the buck-boost converter at low input voltage. in buck mode, the buck-boost output current is limited only by the inductor current reaching the current limit value. however, in boost mode, especially at large step-up ratios, the output current capability can also be limited by the total resistive losses in the power stage. these include switch resistances, inductor resistance and pcb trace resistance. use of an inductor with high dc resistance can degrade the output current capability from that shown in the graph in the typical performance characteristics section of this data sheet. different inductor core materials and styles have an impact on the size and price of an inductor at any given current rating. shielded construction is generally preferred as it minimizes the chances of interference with other circuitry. fb r1 3113 f02 r2 ltc3113 1.8v v out 5.5v sgnd figure 2. setting the output voltage the resistor divider values determine the buck-boost output voltage according to the following formula: v out = 0.600 1 + r2 r1 ? ? ? ? ? ? v () as noted in the current limit operation section: for the current limit feature to be most effected, the thevenin re- sistance (r1||r2) from fb to ground should exceed 100k. inductor selection to achieve high ef? ciency, a low esr inductor should be selected for the buck-boost converter. in addition, the inductor must have a saturation current rating that is greater than the worst-case average inductor current plus half the ripple current. the peak-to-peak inductor current ripple will be larger in buck and boost mode than in the buck-boost region. the peak-to-peak inductor current ripple for each mode can be calculated from the following
ltc3113 13 3113f applications information the choice of inductor style depends upon the price, sizing, and emi requirements of a particular application. table 1 provides a small sampling of inductors that are well suited to many ltc3113 buck-boost converter applications. all inductor speci? cations are listed at an inductance value of 2.2h for comparison purposes but other values within these inductor families are generally well suited to this application. within each family (i.e. at a ? xed size), the dc resistance generally increases and the maximum current generally decreases with increased inductance. table 1. representative buck-boost surface mount inductors part number value (h) dcr (m) max dc current (a) size (mm) w l h coilcraft (www.coilcraft.com) mss1048 2.2 7.2 8.4 10 10.3 4 mss1260 2.2 12 13.9 12.3 12.3 6 ser1052 2.2 4 10 10.6 10.6 5.2 toko (www.toko.com) d106c 2.4 7.7 10 10.3 10.3 6.7 fda1055 2.2 4.8 10.5 11.6 10.8 5.5 fda1254 2.2 4.5 14.7 13.5 12.6 5.4 cooper (www.cooperbussmann.com) hcp0703 2.2 18 14 7 7.3 3 hcp0704 2.3 16.5 11.5 6.8 6.8 4.2 hc8 2.6 11.4 10 10.9 10.4 4 tdk (www.component.tdk.com) vlf100040 2.2 7.9 8.2 9.7 10 4 rlf12560 2.7 4.5 12 13 13 6 vlf12060 2.7 6.4 10 11.7 12 6 wurth (www.we-online.com) 744066 2.2 10.5 6.8 10 10 3.8 744355 2 8 13 13.2 12.8 6.2 744324 2.4 4.8 17 10.5 10.2 4.7 output capacitor selection a low esr output capacitor should be utilized at the buck- boost converter output in order to minimize output voltage ripple. multilayer ceramic capacitors are an excellent choice as they have low esr and are available in small footprints. the capacitor should be chosen large enough to reduce the output voltage ripple to acceptable levels. neglecting the capacitor esr and esl, the peak-to-peak output voltage ripple can be calculated by the following formulas, where f is the frequency in mhz, c out is the capacitance in f, l is the inductance in h, v in is the input voltage in volts, v out is the output voltage in volts. ?v p-p is the output ripple in volts and i load is the output current in amps. c out 1 v p-p,buck ?8?l?f 2 ? v in ?v out () ?v out v in f () c out i load v out ?v in () v p-p,boost ?v out ?f f () given that the output current is discontinuous in boost mode, the ripple in this mode will generally be much larger than the magnitude of the ripple in buck mode. input capacitor selection it is recommended that a low esr ceramic capacitor with a value of at least 47f be located as close to v in as possible. in addition, the return trace from the pin to the ground plane should be made as short as possible. it is important to minimize any stray resistance from the converter to the battery or other power sources. if cabling is required to connect the ltc3113 to the battery or power supply, a higher esr capacitor or a series resistor with low esr capacitor in parallel with the low esr capacitor may be needed to damp out ringing caused by the cable inductance. capacitor vendor information both the input bypass capacitors and output capacitors used with the ltc3113 must be low esr and designed to handle the large ac currents generated by switching converters. this is important to maintain proper functioning of the ic and to reduce output ripple. many modern low voltage ceramic capacitors experience signi? cant loss in capacitance from their rated value with increased dc bias voltages. for example, it is not uncommon for a small surface mount ceramic capacitor to lose 50% or more of its rated capacitance when operated near its rated voltage. as a result, it is sometimes necessary to use a larger value capacitance or a capacitor with a higher voltage rating than required in order to actually realize the intended capacitance at the full operating voltage. for details, consult the capacitor vendors curve of capacitance versus dc bias voltage.
ltc3113 14 3113f applications information the capacitors listed in table 2 provide a sampling of small surface mount ceramic capacitors that are well suited to ltc3113 application circuits. all listed capacitors are either x5r or x7r dielectric in order to ensure that capacitance loss over temperature is minimized. table 2. representative buck-boost surface input mount bypass and output capacitors part number value (f) voltage (v) size (mm) w l h (footprint) avx (www.avx.com) 1812d476kat2a 47 6.3 3.2 4.5 2.5 (1812) 18126d107kat2a 100 6.3 3.2 4.5 2.8 (1812) murata (www.murata.com) grm43er60j476me01 47 6.3 3.2 4.5 2.5 (1812) grm43sr60j107me20 100 6.3 3.2 4.5 2.8 (1812) grm55fr60j107ka01l 100 6.3 5 5.7 3.2 (2220) taiyo yuden (www.t-yuden.com) jmk432bj476mm-t 47 6.3 3.2 4.5 2.5 (1812) jmk432c107mm-t 100 6.3 3.2 4.5 2.8 (1812) tdk (www.component.tdk.com) c4532x5r0j476m 47 6.3 3.2 4.5 2.5 (1812) c4532x5r0j107m 100 6.3 3.2 4.5 2.5 (1812) c5750x5r1c476m 47 16 5 5.7 2.5 (2220) c5750x5r1a686m 68 10 5 5.7 2.5 (2220) c5750x5r0j107m 100 6.3 5 5.7 2.5 (2220) pcb layout considerations the ltc3113 switches large currents at high frequencies. special attention should be paid to the pcb layout to ensure a stable, noise-free and ef? cient application circuit. figure 3 presents a representative 4-layer pcb layout to outline some of the primary considerations. a few key guidelines are outlined below: 1. all circulating high current paths should be kept as short as possible. this can be accomplished by keeping the routes to all highlighted components in figure 3 as short and as wide as possible. capacitor ground connections should via down to the ground plane in the shortest route possible. the bypass capacitors on v in should be placed as close to the ic as possible and should have the shortest possible paths to ground. 2. the exposed pad is the power ground connection for the ltc3113. multiple vias should connect the backpad directly to the ground plane. in addition maximization of the metallization connected to the backpad will im- prove the thermal environment and improve the power handling capabilities of the ic. refer to figure 3d bot- tom layer as an example of proper exposed pad power ground and via layout to provide good thermal and ground connection performance. 3. the components shown highlighted and their connec- tions should all be placed over a complete ground plane to minimize loop cross-sectional areas. this minimizes emi and reduces inductive drops. 4. connections to all of the components shown highlighted should be made as wide as possible to reduce the series resistance. this will improve ef? ciency and maximize the output current capability of the buck-boost converter. 5. to prevent large circulating currents from disrupting the output voltage sensing, the ground for each resistor divider should be returned to the ground plane using a via placed close to the ic and away from the power connections. 6. keep the connection from the resistor dividers to the feedback pins, fb, as short as possible and away from the switch pin connections. 7. crossover connections should be made on inner copper layers if available. if it is necessary to place these on the ground plane, make the trace on the ground plane as short as possible to minimize the disruption to the ground plane. thermal considerations the ltc3113 output current may need to be derated if it is required to operate in a high ambient temperature or delivering a large amount of continuous power. the amount of current derating is dependent upon the input voltage, output voltage and ambient temperature. the temperature rise curves given in the typical performance characteristics section can be used as a guide. these curves were generated by mounting the ltc3113 to a 4-layer fr4 demo board shown in figure 3. boards of other sizes and layer count can exhibit different thermal behavior, so
ltc3113 15 3113f applications information sw1 12 13 14 15 16 1 c1 33pf c5 1f c2 100f 6.3v c3 1f 6.3v v out 3.3v gnd e1 e2 r3 10k r2 715k 1% r7 158k 1% 3113 f03a 3 4 5 11 7 8 2 3 1 617 2 10 9 gnd r5 10k r9 1.0m jp1 pwm v in v in v out burst mode operation on off fixed frequency c8 680pf c9 10pf v in v in v in run burst rt v out v out fb vc sw1 sw1 ltc3113edhd sw2 l1 2.2h sgnd pgnd sw2 r8 90.9k 1% 2 3 1 jp2 c7 68f 10v v in 1.8v to 5.5v gnd e3 e4 r4 1m figure 3b. fabrication layer of example pcb figure 3a
ltc3113 16 3113f it is incumbent upon the user to verify proper operation over the intended systems line, load and environmental operating conditions. the junction-to-air ( ja ) and junction-to-case ( jc ) thermal resistance given in the pin con? guration diagram may also be used to estimate the ltc3113 internal temperature. these thermal coef? cients are determined using a 4-layer pcb. bear in mind that the actual thermal resistance of the ltc3113 to the printed circuit board depends upon the design of the circuit board. the die temperature of the ltc3113 must be lower than the maximum rating of 125c, so care should be taken in the layout of the circuit board to ensure good heat sinking of the ltc3113. the bulk of the heat ? ow is through the bottom exposed pad of the part into the printed circuit board. consequently, a poor printed circuit board design can cause excessive heating, resulting in impaired performance or reliability. refer to the pcb layout considerations section for printed circuit board design suggestions. as described in the thermal shutdown section, the ltc3113 is equipped with a thermal shutdown circuit that will inhibit power switching at high junction temperatures. the activation threshold of this function, however, is above the 125c rating to avoid interfering with normal operation. thus, it follows that prolonged or repetitive operation under a condition in which the thermal shutdown activates necessarily means that the die is subjected to temperatures above the 125c rating for prolonged or repetitive intervals, which may damage or impair the reliability of the device. figure 3c. top layer of example pcb figure 3d. bottom layer of example pcb thermal and pgnd vias applications information
ltc3113 17 3113f applications information closing the feedback loop the ltc3113 incorporates voltage mode pwm control. the control-to-output gain varies with the operation region (buck, buck-boost, boost), but is usually no greater than 15. the output ? lter exhibits a double pole response, as given by: f filter _ pole = 1 2 lc out hz () in buck region () f filter _ pole = 1 2 lc out v in v out hz () in boost region () where l is in henries and c out is in farads. the output ? lter zero is given by: f filter _ zero = 1 2 r esr c out hz () where r esr is the equivalent series resistance out the output capacitor in ohms. a troublesome feature in the boost and buck-boost region is the right-half plane (rhp) zero, given by: f rhpz = v in 2 2 i out lv out hz () the loop gain is typically rolled off before the rhp zero frequency. a simple type i compensation network can be incorporated to stabilize the loop at the cost of reduced bandwidth and slower transient response. to ensure proper phase margin using type i compensation, the loop must be crossed over a decade before the lc double pole. referring to figure 4, the unity-gain frequency of the error ampli? er with the type i compensation is given by: f ug = 1 2 r2c p1 hz () C + error amp 0.6v r1 r2 fb v out vc 3113 f04 c p1 figure 4. error ampli? er with type i compensation C + error amp 0.6v r1 r2 r p fb v out vc 3113 f05 c p2 c z1 r z c p1 figure 5. error ampli? er with type iii compensation most applications demand an improved transient response to allow a smaller output capacitor. to achieve a higher bandwidth, type iii compensation is required, providing two zeros to compensate for the double-pole response of the output ? lter. referring to figure 5, the location of the poles and zeros are given by: f pole1 = 1 2 10 5 r2c p1 hz () f zero1 = 1 2 r z c p1 hz () f zero2 = 1 2 r2c z1 hz () f pole2 = 1 2 r z c p2 hz () f pole3 = 1 2 r p c z1 hz () where resistance is in ohms and capacitance is in farads.
ltc3113 18 3113f typical applications li-ion to 3.3v/3a sw1 v in v out ltc3113 2.2h run 47f 100f v out 3.3v 3a v in 2.5v to 4.2v li-ion burst off on pwm burst fb vc 49.9k 825k 680pf 12pf 90.9k rt sw2 sgnd pgnd 182k 3113 ta02a 6.49k 47pf ef? ciency li-ion (3v, 3.7v, 4.2v) to 3.3v load current (a) efficiency (%) 70 80 90 100 0.001 0.1 1 10 3113 ta02b 60 0.01 v in = 3v v in = 3.7v v in = 4.2v v in = 3v burst v in = 3.7v burst v in = 4.2v burst power loss li-ion (3v, 3.7v, 4.2v) to 3.3v load current (a) power loss (w) 0.001 0.01 0.1 1 10 0.001 0.1 1 10 3113 ta02c 0.0001 0.01 v in = 3v v in = 3.7v v in = 4.2v pwm mode burst mode operation
ltc3113 19 3113f typical applications typical output response with 1.5a load sw1 v in v out ltc3113 2.2h run 30f 0.1f 30f 100f v out 3.3v v in 1.8v to 4.5v burst off on pwm burst fb vc 49.9k 825k 680pf 12pf 90.9k rt sw2 sgnd pgnd 182k 3113 ta03a 6.49k 47pf supercap powered backup supply v out 2v/div v in 2v/div run 2v/div 5 sec/div 3113 ta03b
ltc3113 20 3113f typical applications 3.3v to 5v/2.5a boost converter with output disconnect ef? ciency vs load current sw1 v in v out ltc3113 2.2h run 47f 100f 5v v in 3.3v 10% burst off on pwm burst fb vc 49.9k 887k 680pf 12pf 90.9k rt sw2 sgnd pgnd 121k 3113 ta04a 6.49k 47pf load current (a) 60 efficiency (%) 70 80 90 100 0.001 0.1 1 10 3113 ta04b 50 0.01 burst mode operation pwm mode power loss vs load current burst mode operation load current (a) power loss (w) 0.01 0.1 1 10 0.001 0.1 1 10 3113 ta04c 0.001 0.01 pwm mode
ltc3113 21 3113f typical applications 3.3v to 1.8v/5a buck converter sw1 v in v out ltc3113 2.2h run 47f 100f v out 1.8v v in 3.3v 10% burst off on pwm burst fb vc 49.9k 665k 680pf 12pf 90.9k rt sw2 sgnd pgnd 332k 3113 ta05a 6.49k 47pf ef? ciency vs load current load current (a) 60 efficiency (%) 70 80 90 100 0.001 0.1 1 10 3113 ta05b 50 0.01 burst mode operation pwm mode power loss vs load current load current (a) 0.001 power loss (w) 0.01 0.1 1 10 0.001 0.1 1 10 3113 ta06 0.0001 0.01 burst mode operation pwm mode
ltc3113 22 3113f dhd package 16-lead plastic dfn (5mm 4mm) (reference ltc dwg # 05-08-1707) 4.00 p0.10 (2 sides) 5.00 p0.10 (2 sides) note: 1. drawing proposed to be made variation of version (wjgd-2) in jedec package outline mo-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 p 0.10 bottom viewexposed pad 2.44 p 0.10 (2 sides) 0.75 p0.05 r = 0.115 typ r = 0.20 typ 4.34 p0.10 (2 sides) 1 8 16 9 pin 1 top mark (see note 6) 0.200 ref 0.00 C 0.05 (dhd16) dfn 0504 0.25 p 0.05 pin 1 notch 0.50 bsc 4.34 p0.05 (2 sides) recommended solder pad pitch and dimensions 2.44 p0.05 (2 sides) 3.10 p0.05 0.50 bsc 0.70 p0.05 4.50 p0.05 package outline 0.25 p 0.05 package description
ltc3113 23 3113f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description fe package 20-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663) exposed pad variation ca fe20 (ca) tssop 0204 0.09 C 0.20 (.0035 C .0079) 0o C 8o 0.25 ref recommended solder pad layout 0.50 C 0.75 (.020 C .030) 4.30 C 4.50* (.169 C .177) 134 5 6 7 8910 111214 13 6.40 C 6.60* (.252 C .260) 4.95 (.195) 2.74 (.108) 20 1918 17 16 15 1.20 (.047) max 0.05 C 0.15 (.002 C .006) 0.65 (.0256) bsc 0.195 C 0.30 (.0077 C .0118) typ 2 2.74 (.108) 0.45 p0.05 0.65 bsc 4.50 p0.10 6.60 p0.10 1.05 p0.10 4.95 (.195) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc
ltc3113 24 3113f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com linear technology corporation 2010 lt 1110 ? printed in usa related parts typical application pulsed load or portable rf power ampli? er application typical output response part number description comments ltc3112 15v, 2.5a (i out ) synchronous buck-boost dc/dc converter v in : 2.7v to 15v, v out : 2.5v to 14v, i q = 50a, i sd < 1a, dfn package ltc3127 1a buck-boost dc/dc converter with programmable input current limit v in : 1.8v to 5.5v, v out : 1.8v to 5.25v, i q = 35a, i sd < 1a, dfn package ltc3531 200ma buck-boost synchronous dc/dc converter v in : 1.8v to 5.5v, v out = 3.3v, i q =16a, i sd < 1a, dfn package ltc3533 2a (i out ), 2mhz synchronous buck-boost dc/dc converter v in : 1.8v to 5.5v, v out : 1.8v to 5.25v, i q = 40a, i sd < 1a, dfn package ltc3534 7v, 500ma synchronous buck-boost dc/dc converter v in : 2.4v to 7v, v out : 1.8v to 7v, i q = 25a, i sd < 1a, dfn package ltc3440 600ma (i out ), 2mhz synchronous buck-boost dc/dc converter v in : 2.5v to 5.5v, v out : 2.5v to 5.25v, i q = 25a, i sd < 1a, msop and dfn packages ltc3441 1.2a (i out ), 1mhz synchronous buck-boost dc/dc converter v in : 2.4v to 5.5v, v out : 2.4v to 5.25v, i q = 25a, i sd < 1a, dfn package ltc3442 1.2a (i out ), 2mhz synchronous buck-boost dc/dc converter with programmable burst mode operation v in : 2.4v to 5.5v, v out : 2.4v to 5.25v, i q = 35a, i sd < 1a, dfn package ltc3785 10v, high ef? ciency, synchronous, no r sense ? buck-boost controller v in : 2.7v to 10v, v out : 2.7v to 10v, i q = 86a, i sd < 15a, qfn package ltc3101 wide v in , multi-output dc/dc converter and powerpath? controller v in : 1.8v to 5.5v, v out : 1.5v to 5.25v, i q = 38a, i sd < 15a, qfn package ltc3530 wide input voltage synchronous buck-boost dc/dc converter v in : 1.8v to 5.5v, v out : 1.8v to 5.25v, i q = 40a, i sd < 1a, dfn package sw1 v in v out ltc3113 2.2h run 47f 4.7f 200f 4.7f v out 3.8v 0a to 3a v in 3.3v 10% burst off on pwm burst fb vc 68k 845k 220pf 10pf 90.9k rt sw2 sgnd pgnd 158k 3113 ta06a 10k 33pf v out 200mv/div i load 2a/div 100s/div 3113 ta06b

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